// -*- mode:c++ -*-

// Copyright (c) 2010-2013, 2016 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder.  You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

let {{
    vfpEnabledCheckCode = '''
    {
        Fault fault = checkAdvSIMDOrFPEnabled32(xc->tcBase(),
                                                Cpsr, Cpacr, Nsacr, Fpexc,
                                                true, false);
        if (fault != NoFault)
            return fault;
    }
    '''

    vfp64EnabledCheckCode = '''
    {
        Fault fault = checkFPAdvSIMDEnabled64(xc->tcBase(), Cpsr, Cpacr64);
        if (fault != NoFault)
             return fault;
    }
    '''

    vmsrEnabledCheckCode = '''
    {
        Fault fault = NoFault;
        if (dest == (int)MISCREG_FPSCR) {
            fault = checkAdvSIMDOrFPEnabled32(xc->tcBase(),
                                              Cpsr, Cpacr, Nsacr, Fpexc,
                                              true, false);
        } else if (!inPrivilegedMode(Cpsr)) {
            fault = disabledFault();
        } else {
            fault = checkAdvSIMDOrFPEnabled32(xc->tcBase(),
                                              Cpsr, Cpacr, Nsacr, Fpexc,
                                              false, false);
        }

        if (fault != NoFault)
            return fault;
    }
    '''

    vmrsEnabledCheckCode = '''
    {
        Fault fault = NoFault;
        if (op1 == (int)MISCREG_FPSCR) {
            fault = checkAdvSIMDOrFPEnabled32(xc->tcBase(),
                                              Cpsr, Cpacr, Nsacr, Fpexc,
                                              true, false);
        } else if (!inPrivilegedMode(Cpsr)) {
            fault = disabledFault();
        } else {
            fault = checkAdvSIMDOrFPEnabled32(xc->tcBase(),
                                              Cpsr, Cpacr, Nsacr, Fpexc,
                                              false, false);
        }

        if (fault != NoFault)
            return fault;
    }
    '''
}};

def template FpRegRegOpDeclare {{
class %(class_name)s : public %(base_class)s
{
  private:
    %(reg_idx_arr_decl)s;

  public:
    // Constructor
    %(class_name)s(ExtMachInst machInst,
                   RegIndex _dest, RegIndex _op1,
                   VfpMicroMode mode = VfpNotAMicroop);
    Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};

def template FpRegRegOpConstructor {{
    %(class_name)s::%(class_name)s(ExtMachInst machInst,
                                          RegIndex _dest, RegIndex _op1,
                                          VfpMicroMode mode)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                _dest, _op1, mode)
    {
        %(set_reg_idx_arr)s;
        %(constructor)s;
        if (!(condCode == COND_AL || condCode == COND_UC)) {
            for (int x = 0; x < _numDestRegs; x++) {
                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
            }
        }
    }
}};

def template FpRegImmOpDeclare {{
class %(class_name)s : public %(base_class)s
{
  private:
    %(reg_idx_arr_decl)s;

  public:
    // Constructor
    %(class_name)s(ExtMachInst machInst, RegIndex _dest,
            uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop);
    Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};

def template FpRegImmOpConstructor {{
    %(class_name)s::%(class_name)s(ExtMachInst machInst,
            RegIndex _dest, uint64_t _imm, VfpMicroMode mode)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                _dest, _imm, mode)
    {
        %(set_reg_idx_arr)s;
        %(constructor)s;
        if (!(condCode == COND_AL || condCode == COND_UC)) {
            for (int x = 0; x < _numDestRegs; x++) {
                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
            }
        }
    }
}};

def template FpRegRegImmOpDeclare {{
class %(class_name)s : public %(base_class)s
{
  private:
    %(reg_idx_arr_decl)s;

  public:
    // Constructor
    %(class_name)s(ExtMachInst machInst,
                   RegIndex _dest, RegIndex _op1,
                   uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop);
    Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};

def template FpRegRegImmOpConstructor {{
    %(class_name)s::%(class_name)s(ExtMachInst machInst,
                                          RegIndex _dest,
                                          RegIndex _op1,
                                          uint64_t _imm,
                                          VfpMicroMode mode)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                         _dest, _op1, _imm, mode)
    {
        %(set_reg_idx_arr)s;
        %(constructor)s;
        if (!(condCode == COND_AL || condCode == COND_UC)) {
            for (int x = 0; x < _numDestRegs; x++) {
                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
            }
        }
    }
}};

def template FpRegRegRegOpDeclare {{
class %(class_name)s : public %(base_class)s
{
  private:
    %(reg_idx_arr_decl)s;

  public:
    // Constructor
    %(class_name)s(ExtMachInst machInst,
                   RegIndex _dest, RegIndex _op1, RegIndex _op2,
                   VfpMicroMode mode = VfpNotAMicroop);
    Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};

def template FpRegRegRegOpConstructor {{
    %(class_name)s::%(class_name)s(ExtMachInst machInst,
                                          RegIndex _dest,
                                          RegIndex _op1,
                                          RegIndex _op2,
                                          VfpMicroMode mode)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                         _dest, _op1, _op2, mode)
    {
        %(set_reg_idx_arr)s;
        %(constructor)s;
        if (!(condCode == COND_AL || condCode == COND_UC)) {
            for (int x = 0; x < _numDestRegs; x++) {
                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
            }
        }
    }
}};

def template FpRegRegRegCondOpDeclare {{
class %(class_name)s : public %(base_class)s
{
  private:
    %(reg_idx_arr_decl)s;

  public:
    // Constructor
    %(class_name)s(ExtMachInst machInst,
                   RegIndex _dest, RegIndex _op1, RegIndex _op2,
                  ConditionCode _cond,
                   VfpMicroMode mode = VfpNotAMicroop);
    Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};

def template FpRegRegRegCondOpConstructor {{
    %(class_name)s::%(class_name)s(ExtMachInst machInst,
                                          RegIndex _dest,
                                          RegIndex _op1,
                                          RegIndex _op2,
                                          ConditionCode _cond,
                                          VfpMicroMode mode)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                         _dest, _op1, _op2, _cond, mode)
    {
        %(set_reg_idx_arr)s;
        %(constructor)s;
    }
}};
